disassembler, assembler, bug fixes, and more
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@@ -96,6 +96,8 @@ enum instruction {
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LD_PTR_I_REG,
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// operand is a pointer to a uint8_t
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LD_REG_PTR_I,
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// no operand
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HLT,
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UNKNOWN_INSTRUCTION,
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};
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@@ -136,11 +138,16 @@ inline Bytecode parse(uint16_t opcode) {
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bytecode.instruction_type = RET;
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break;
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}
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case 0x0000: {
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// HLT 0x0000
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bytecode.instruction_type = HLT;
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break;
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}
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default:
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// SYS NNN
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//? NOTE: This is an outdated opcode, but it's still
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//? important for completeness. It's not clear what the
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//? difference is between it and the JMP NNN 0x1NNN opcode.
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//? difference is between it and the JP NNN 0x1NNN opcode.
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bytecode.instruction_type = SYS;
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break;
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}
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@@ -207,7 +214,7 @@ inline Bytecode parse(uint16_t opcode) {
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// meant set VX equal to VY bitshifted right 1 but emulators and
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// software seem to ignore VY now. Note: This instruction was
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// originally undocumented but functional due to how the 8XXX
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// instructions were implemented on teh COSMAC VIP.
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// instructions were implemented on the COSMAC VIP.
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bytecode.instruction_type = SHR_REG;
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break;
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}
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@@ -316,6 +323,7 @@ inline Bytecode parse(uint16_t opcode) {
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switch (bytecode.instruction_type) {
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case UNKNOWN_INSTRUCTION:
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case HLT:
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case RET:
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case CLS: {
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// no operand
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