a lot of stuff, but mainly, a decent allocator
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@@ -2,10 +2,7 @@ use crate::{drivers::acpi::SMP_REQUEST, hcf, libs::cell::OnceCell};
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use alloc::{sync::Arc, vec::Vec};
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use super::super::{
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cpu_get_msr, cpu_set_msr,
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io::{inb, outb},
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};
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use super::super::{cpu_get_msr, cpu_set_msr, io::outb};
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#[repr(C, packed)]
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#[derive(Clone, Copy, Debug)]
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@@ -107,33 +104,41 @@ impl APIC {
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let ptr_end = unsafe { ptr.add(madt.header.length as usize - 44) };
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while (ptr as usize) < (ptr_end as usize) {
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match unsafe { *ptr } {
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// ptr may or may bot be aligned, although I have had crashes related to this pointer being not aligned
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// and tbh I dont really care about the performance impact of reading unaligned pointers right now
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// TODO
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match unsafe { core::ptr::read_unaligned(ptr) } {
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0 => {
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if unsafe { *(ptr.add(4)) } & 1 != 0 {
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cpus.push(unsafe { *ptr.add(2).cast::<LAPIC>() });
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cpus.push(unsafe { core::ptr::read_unaligned(ptr.add(2).cast::<LAPIC>()) });
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}
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}
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1 => unsafe {
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io_apic = Some(IOAPIC {
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ioapic_id: *ptr.add(2),
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_reserved: *ptr.add(3),
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ptr: (*ptr.add(4).cast::<u32>()) as *mut u8,
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global_interrupt_base: *ptr.add(8).cast::<u32>(),
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ioapic_id: core::ptr::read_unaligned(ptr.add(2)),
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_reserved: core::ptr::read_unaligned(ptr.add(3)),
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ptr: (core::ptr::read_unaligned(ptr.add(4).cast::<u32>())) as *mut u8,
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global_interrupt_base: core::ptr::read_unaligned(ptr.add(8).cast::<u32>()),
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})
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},
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2 => unsafe {
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io_apic_source_override = Some(IOAPICSourceOverride {
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bus_source: *ptr.add(2),
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irq_source: *ptr.add(3),
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global_system_interrupt: *ptr.add(4).cast::<u32>(),
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flags: *ptr.add(8).cast::<u16>(),
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bus_source: core::ptr::read_unaligned(ptr.add(2)),
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irq_source: core::ptr::read_unaligned(ptr.add(3)),
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global_system_interrupt: core::ptr::read_unaligned(
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ptr.add(4).cast::<u32>(),
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),
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flags: core::ptr::read_unaligned(ptr.add(8).cast::<u16>()),
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})
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},
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5 => lapic_ptr = unsafe { *(ptr.add(4).cast::<u64>()) } as *mut u8,
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5 => {
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lapic_ptr =
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unsafe { core::ptr::read_unaligned(ptr.add(4).cast::<u64>()) } as *mut u8
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}
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_ => {}
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}
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ptr = unsafe { ptr.add((*ptr.add(1)) as usize) };
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ptr = unsafe { ptr.add(core::ptr::read_unaligned(ptr.add(1)) as usize) };
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}
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if io_apic.is_none() || io_apic_source_override.is_none() {
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@@ -168,10 +173,6 @@ impl APIC {
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crate::println!("{number_of_inputs}");
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// // hopefully nothing important is on that page :shrug:
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// // TODO: use the page allocator we wrote maybe
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// unsafe { core::ptr::copy(test as *mut u8, 0x8000 as *mut u8, 4096) }
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let smp_request = SMP_REQUEST.get_response().get_mut();
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if smp_request.is_none() {
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@@ -189,82 +190,12 @@ impl APIC {
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cpu.goto_address = test;
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}
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// for cpu_apic in apic.cpus.iter() {
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// let lapic_id = cpu_apic.apic_id;
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// // TODO: If CPU is the BSP, do not intialize it
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// crate::log_info!("Initializing CPU {processor_id:<02}, please wait",);
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// match apic.bootstrap_processor(processor_id, 0x8000) {
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// Err(_) => crate::log_error!("Failed to initialize CPU {processor_id:<02}!"),
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// Ok(_) => crate::log_ok!("Successfully initialized CPU {processor_id:<02}!"),
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// }
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// }
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// Set and enable keyboard interrupt
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apic.set_interrupt(0x01, 0x01);
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return Ok(apic);
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}
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// pub fn bootstrap_processor(&self, processor_id: u8, startup_page: usize) -> Result<(), ()> {
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// // Clear LAPIC errors
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// self.write_lapic(0x280, 0);
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// // Select Auxiliary Processor
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// self.write_lapic(
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// 0x310,
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// (self.read_lapic(0x310) & 0x00FFFFFF) | (processor_id as u32) << 24,
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// );
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// // send INIT Inter-Processor Interrupt
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// self.write_lapic(0x300, (self.read_lapic(0x300) & 0x00FFFFFF) | 0x00C500);
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// // Wait for IPI delivery
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// while self.read_lapic(0x300) & (1 << 12) != 0 {
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// unsafe {
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// core::arch::asm!("pause");
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// }
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// }
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// // Select Auxiliary Processor
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// self.write_lapic(
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// 0x310,
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// (self.read_lapic(0x310) & 0x00FFFFFF) | (processor_id as u32) << 24,
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// );
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// // deassert
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// self.write_lapic(0x300, (self.read_lapic(0x300) & 0x00FFFFFF) | 0x00C500);
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// // Wait for IPI delivery
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// while self.read_lapic(0x300) & (1 << 12) != 0 {
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// unsafe {
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// core::arch::asm!("pause");
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// }
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// }
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// msdelay(10);
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// for i in 0..2 {
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// self.write_lapic(0x280, 0);
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// self.write_lapic(
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// 0x310,
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// (self.read_lapic(0x310) & 0x00FFFFFF) | (processor_id as u32) << 24,
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// );
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// self.write_lapic(0x300, (self.read_lapic(0x300) & 0xfff0f800) | 0x000608);
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// if i == 0 {
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// usdelay(200);
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// } else {
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// msdelay(1000);
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// }
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// while self.read_lapic(0x300) & (1 << 12) != 0 {
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// unsafe {
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// core::arch::asm!("pause");
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// }
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// }
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// }
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// return Ok(());
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// }
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pub fn read_ioapic(&self, reg: u32) -> u32 {
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unsafe {
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core::ptr::write_volatile(self.io_apic.ptr.cast::<u32>(), reg & 0xff);
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@@ -336,40 +267,41 @@ fn disable_pic() {
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outb(PIC_DATA_SLAVE, 0xFF);
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}
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pub fn usdelay(useconds: u16) {
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let pit_count = ((useconds as u32 * 1193) / 1000) as u16;
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// // TODO: last I remember these didnt work
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// pub fn usdelay(useconds: u16) {
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// let pit_count = ((useconds as u32 * 1193) / 1000) as u16;
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pit_delay(pit_count);
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}
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// pit_delay(pit_count);
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// }
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pub fn msdelay(ms: u32) {
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let mut total_count = ms * 1193;
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// pub fn msdelay(ms: u32) {
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// let mut total_count = ms * 1193;
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while total_count > 0 {
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let chunk_count = if total_count > u16::MAX as u32 {
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u16::MAX
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} else {
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total_count as u16
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};
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// while total_count > 0 {
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// let chunk_count = if total_count > u16::MAX as u32 {
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// u16::MAX
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// } else {
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// total_count as u16
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// };
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pit_delay(chunk_count);
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// pit_delay(chunk_count);
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total_count -= chunk_count as u32;
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}
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}
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// total_count -= chunk_count as u32;
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// }
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// }
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pub fn pit_delay(count: u16) {
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// Set PIT to mode 0
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outb(0x43, 0x30);
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outb(0x40, (count & 0xFF) as u8);
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outb(0x40, ((count & 0xFF00) >> 8) as u8);
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loop {
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// Tell PIT to give us a timer status
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outb(0x43, 0xE2);
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if ((inb(0x40) >> 7) & 0x01) != 0 {
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break;
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}
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}
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}
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// pub fn pit_delay(count: u16) {
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// // Set PIT to mode 0
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// outb(0x43, 0x30);
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// outb(0x40, (count & 0xFF) as u8);
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// outb(0x40, ((count & 0xFF00) >> 8) as u8);
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// loop {
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// // Tell PIT to give us a timer status
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// outb(0x43, 0xE2);
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// if ((inb(0x40) >> 7) & 0x01) != 0 {
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// break;
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// }
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// }
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// }
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pub static APIC: OnceCell<APIC> = OnceCell::new();
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