add riscv files

src/arch/riscv64/io.rs

@@ -0,0 +1,54 @@
+#[inline(always)]
+pub fn outb(port: u16, value: u8) {
+    return;
+}
+
+#[inline(always)]
+pub fn inb(port: u16) -> u8 {
+    return 0;
+}
+
+#[inline(always)]
+pub fn outw(port: u16, value: u16) {
+    return;
+}
+
+#[inline(always)]
+pub fn inw(port: u16) -> u16 {
+    return 0;
+}
+
+/// Reads `count` 16-bit values from the specified `port` into the `buffer`.
+///
+/// # Safety
+///
+/// This function panics if the supplied buffer's size is smaller than `count`.
+#[inline(always)]
+pub unsafe fn insw(port: u16, buffer: *mut u16, count: usize) {
+    return;
+}
+
+/// Outputs `count` 16-bit values from the specified `port` into the `buffer`.
+///
+/// # Safety
+///
+/// This function panics if the supplied buffer's size is smaller than `count`.
+#[inline(always)]
+pub unsafe fn outsw(port: u16, buffer: *mut u16, count: usize) {
+    return;
+}
+
+#[inline(always)]
+pub fn outl(port: u16, value: u32) {
+    return;
+}
+
+#[inline(always)]
+pub fn inl(port: u16) -> u32 {
+    return 0;
+}
+
+#[inline(always)]
+pub fn io_wait() {
+    return;
+}

src/arch/riscv64/linker.ld

@@ -0,0 +1,65 @@
+/* Tell the linker that we want a riscv64 ELF64 output file */
+OUTPUT_FORMAT(elf64-littleriscv)
+OUTPUT_ARCH(riscv:rv64)
+
+/* We want the symbol _start to be our entry point */
+ENTRY(_start)
+
+/* Define the program headers we want so the bootloader gives us the right */
+/* MMU permissions */
+PHDRS
+{
+    text    PT_LOAD    FLAGS((1 << 0) | (1 << 2)) ; /* Execute + Read */
+    rodata  PT_LOAD    FLAGS((1 << 2)) ;            /* Read only */
+    data    PT_LOAD    FLAGS((1 << 1) | (1 << 2)) ; /* Write + Read */
+    dynamic PT_DYNAMIC FLAGS((1 << 1) | (1 << 2)) ; /* Dynamic PHDR for relocations */
+}
+
+SECTIONS
+{
+    /* We wanna be placed in the topmost 2GiB of the address space, for optimisations */
+    /* and because that is what the Limine spec mandates. */
+    /* Any address in this region will do, but often 0xffffffff80000000 is chosen as */
+    /* that is the beginning of the region. */
+    . = 0xffffffff80000000;
+
+    .text : {
+        *(.text .text.*)
+    } :text
+
+    /* Move to the next memory page for .rodata */
+    . += CONSTANT(MAXPAGESIZE);
+
+    .rodata : {
+        *(.rodata .rodata.*)
+    } :rodata
+
+    /* Move to the next memory page for .data */
+    . += CONSTANT(MAXPAGESIZE);
+
+    .data : {
+        *(.data .data.*)
+        *(.sdata .sdata.*)
+    } :data
+
+    /* Dynamic section for relocations, both in its own PHDR and inside data PHDR */
+    .dynamic : {
+        *(.dynamic)
+    } :data :dynamic
+
+    /* NOTE: .bss needs to be the last thing mapped to :data, otherwise lots of */
+    /* unnecessary zeros will be written to the binary. */
+    /* If you need, for example, .init_array and .fini_array, those should be placed */
+    /* above this. */
+    .bss : {
+        *(.sbss .sbss.*)
+        *(.bss .bss.*)
+        *(COMMON)
+    } :data
+
+    /* Discard .note.* and .eh_frame since they may cause issues on some hosts. */
+    /DISCARD/ : {
+        *(.eh_frame)
+        *(.note .note.*)
+    }
+}

src/arch/riscv64/mod.rs

@@ -0,0 +1 @@
+pub mod io;

src/arch/riscv64/riscv64-unknown-none.json

@@ -0,0 +1,29 @@
+{
+    "code-model": "medium",
+    "cpu": "generic-rv64",
+    "data-layout": "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
+    "llvm-target": "riscv64",
+    "target-endian": "little",
+    "target-pointer-width": "64",
+    "target-c-int-width": "32",
+    "max-atomic-width": "64",
+    "features": "+m,+a,+f,+d,+c",
+    "os": "CappuccinOS",
+    "arch": "riscv64",
+    "linker": "rust-lld",
+    "linker-flavor": "ld.lld",
+    "pre-link-args": {
+        "ld.lld": [
+            "-melf64lriscv",
+            "--script=./src/arch/riscv64/linker.ld"
+        ]
+    },
+    "has-rpath": true,
+    "dynamic-linking": true,
+    "llvm-abiname": "lp64d",
+    "panic-strategy": "abort",
+    "relocation-model": "static",
+    "eh-frame-header": false,
+    "exe-suffix": ".elf",
+    "executables": true
+}